APEC: 1MHz active clamp flyback chipset and 6-A three-level buck battery buck.

Cypress said it uses PSoC 6's dual Cortex-M cores in combination with configurable memory and peripheral protection units to achieve the highest level of protection defined by PSA. The MCU provides three hardware-based isolation levels to reduce the threat attack surface: Use dedicated Cortex-M0 + core to provide independent execution environment for trusted applications The security element that protects the root of trust operations and system services isolates every trusted application. The ARM core (Cortex-M4) also has a true random number generator (TRNG), a cryptographic accelerator, and a domain for handling insecure applications. Future releases will include trusted launch with multiple images and full PSA API support, including a trusted root installation with secure element capabilities.